The present invention relates to a complementary field effect transistor and its manufacturing method.
Large scale integration circuit (LSI) is provided with many MIS type field effect transistors (MISFETs) which have structures of metal/insulating film/semiconductor. Among MISFETs, MOSFETs using an oxide film as an insulating film have two kinds, one of which is a transistor with an n-type conductivity, and another of which is a transistor with a p-type conductivity is called CMOSFET (complementary MOSFET). CMOSFET complementarily provided with both of the transistors is usually used for LSI as a main element. Currently, the miniaturization of MOSFET is progressing and MOSFET with the gate length of 0.1 micrometers is coming soon. This is because the miniaturization of MOSFET leads to improvement in the speed of an element and leads to reduced power consumption. Moreover, since the footprint of an element is reduced by the miniaturization, many elements can be mounted on the same chip area. Consequently, multi-function LSI can be attained.
However, it is conceivable that pursuit of the miniaturization collides with a big wall bordering on 0.1 micrometers of gate length. This border arises from the limit of reducing the thickness of the gate oxide film.
Conventionally, the gate insulating film of the transistor has been demanded to have the characteristic of having high heat resistance and hardly forming an interface level in a boundary with Si of channel. SiO2 which can satisfy these demands simultaneously also has the characteristic that a thin film can be formed easily controlling sufficiently. Since the relative dielectric constant of SiO2 is low (3.9), it is required that the thickness of SiO2 should be 3 nm or less in order to satisfy the performance of a transistor with gate length 0.1 micrometers or less. However, in such thickness, it becomes a problem that the leak current between the gate and the substrate increases when a carrier carries out direct tunneling. This problem is an essential problem of the gate insulating film using SiO2, and is considered to be unavoidable.
Then, there is also technology of avoiding direct tunneling using material with a larger relative dielectric constant than SiO2. ZrO2, HfO2 or metal oxides such as a silicate which is the compound of Zr (or Hf) and SiO2 may be used as the material as disclosed in Japanese Patent Laid-Open Publication No. 2002-231942. The relative dielectric constant of the metal oxide is as high as about ten or more. Therefore, the thickness of the metal oxide can be made into twice or more of that of SiO2 in order to obtain the same gate capacitance as SiO2. Therefore, the direct tunneling in the gate insulating film can be pressed down.
If bias is applied to a polycrystalline silicon gate electrode, a depletion region will be generated in the gate electrode. The depletion region is mainly produced because the movable carriers at an interface with the gate insulating film are lost by applying the bias. Consequently, since the depletion region functions as an insulator substantially, the capacitance of the gate will fall. The fall of the capacitance of the gate can be avoided by using metal for the gate electrode. When one kind of metal is used for the gate electrodes of the n-type and p-type MOSFETs of CMOSFET, the threshold value of either one of the transistors becomes high, and current can not be obtained. As a result, a problem that the operation of CMOSFET became lower arises.
Although there is also a method of properly using appropriate different metals for the n-type MOSFET and the p-type MOSFET, the manufacturing process may be complicated and may cause a cost rise. Moreover, the method of using different metals may have a practical problem. For example, it is necessary to choose the material which does not cause a reaction mutually as the gate metal of the n-type MOSFET and the gate metal of the p-type MOSFET, or to choose the material with which the gate metal formed previously is not deleted by etching of the gate metal formed afterward.
Furthermore, there is a problem that the appropriate metal materials for the gate electrode of the n-type MOSFET may have another drawback. The appropriate materials for the metal gate electrode of the n-type MOSFET are metals such as Al, Zr, Hf, etc. whose work functions are about 4 eV. Such metals have possibilities that they may become oxides by heat treatment after forming the electrode, and the conductivities may fall rapidly. Moreover, there also may be a problem that gate leak current is raised since the material which is easy to be oxidized reduces the insulating film of the gate. For example, besides Al, the resistivity of Mn is as high as 200 μΩcm, and the silicide such as ErSi2 also tends to be oxidized to the same degree as aluminum etc.
As explained above, conventional CMOSLSI using the metal gate electrode has the problem of causing low-speed operation, when the same metal material is used for the gate electrodes of the n-type and the p-type MOSFETs. Moreover, when different materials are used for the gate electrodes of the n-type and the p-type MOSFETs, there may be problems that the manufacturing process becomes complicated, cost goes up and, no combination of suitable materials is found.